5.03_GAL20V8_883_April

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Specifications	5.03_GAL20V8_883_April_2010 ecoughli
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GAL20V8/883 High Performance E2CMOS PLD Generic Array Logic™ 1 Devices have been discontinued. Features •HIGH PER

Specifications	5.03_GAL20V8_883_April_2010 ecoughli
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Content	GAL20V8/883 High Performance E2CMOS PLD Generic Array Logic™ 1 Devices have been discontinued. Features •HIGH PERFORMANCE E2CMOS® TECHNOLOGY —10 ns Maximum Propagation Delay —Fmax = 62.5 MHz —7 ns Maximum from Clock Input to Data Output —TTL Compatible 12 mA Outputs —UltraMOS® Advanced CMOS Technology •50% REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device •E2 CELL TECHNOLOGY —Reconfigurable Logic —Reprogrammable Cells —100% Tested/100% Yields —High Speed Electrical Erasure (<100ms) —20 Year Data Retention •EIGHT OUTPUT LOGIC MACROCELLS —Maximum Flexibility for Complex Logic Designs —Programmable Output Polarity —Also Emulates 24-pin PAL® Devices with Full Function/ Fuse Map/Parametric Compatibility •PRELOAD AND POWER-ON RESET OF ALL REGISTERS —100% Functional Testability •APPLICATIONS INCLUDE: —DMA Control —State Machine Control —High Speed Graphics Processing —Standard Logic Speed Upgrade •ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL20V8/883 is a high performance E2CMOS program- mable logic devices processed in full compliance to MIL-STD- 883. This military grade device combines a high performance CMOS process with Electrically Erasable (E2) floating gate tech- nology to provide the highest speed/power performance available in the 883 qualified PLD market. The generic GAL architecture provides maximum design flexibil- ity by allowing the Output Logic Macrocell (OLMC) to be config- ured by the user. The GAL20V8/883 is capable of emulating all standard 24-pin PAL® devices with full function/fuse map/para- metric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. 228 NC I/CLK I I I I I I I NCNC NC GND I I I/OE I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I I 4 5 7 9 111214161819 21 23 25 26 GAL20V8 Top View LCC 1 1213 24I/CLK I I I I I I I I I I GND Vcc I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/OE 6 18 GAL 20V8 CERDIP Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.April 2010 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 20v8mil_04 Functional Block Diagram Pin Configuration CLKI I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I I I I I I I I I I/OE I/CLK OE 8 8 8 8 8 8 8 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC IMUX IMUX PROGRAMMABLE AND-ARRAY (64 X 40) OLMC
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