Specifications | 3.09_GAL20LV8 3.09_GAL20LV8 coughlin |
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Specifications | 3.09_GAL20LV8 3.09_GAL20LV8 coughlin |
Business section |
Specifications | 3.09_GAL20LV8 3.09_GAL20LV8 coughlin |
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Content | GAL20LV8 Low Voltage E2CMOS PLD Generic Array Logic™ 120lv8_05 Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.March 2000 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com Features •HIGH PERFORMANCE E2CMOS® TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —2.5 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology —TTL-Compatible Balanced 8mA Output Drive •3.3V LOW VOLTAGE 20V8 ARCHITECTURE —JEDEC-Compatible 3.3V Interface Standard —5V Compatible Inputs •ACTIVE PULL-UPS ON ALL PINS •E2 CELL TECHNOLOGY —Reconfigurable Logic —Reprogrammable Cells —100% Tested/100% Yields —High Speed Electrical Erasure (<100ms) —20 Year Data Retention •EIGHT OUTPUT LOGIC MACROCELLS —Maximum Flexibility for Complex Logic Designs —Programmable Output Polarity •PRELOAD AND POWER-ON RESET OF ALL REGISTERS —100% Functional Testability •APPLICATIONS INCLUDE: —Glue Logic for 3.3V Systems —DMA Control —State Machine Control —High Speed Graphics Processing —Standard Logic Speed Upgrade •ELECTRONIC SIGNATURE FOR IDENTIFICATION 228 NC I/CLK I I I I I I I NCNC NC GND I I I/OE I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I I 4 5 7 9 11 12141618 19 21 23 25 26 GAL20LV8D Top View CLKI I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I I I I I I I I I I/OE I/CLK OE 8 8 8 8 8 8 8 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC IMUX IMUX PROGRAMMABLE AND-ARRAY (64 X 40) OLMC PLCC New 5VTolerantInputs on 20LV8D Description The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor s advanced 3.3V E2CMOS process, which com- bines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be repro- grammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura- tions possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Functional Block Diagram Pin Configuration Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm |
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Following Datasheets | 20lv8zd (19 pages) 20ra10 (16 pages) 20v8 (27 pages) 20v8883 (6 pages) 20v8zzd (20 pages) 20vapec2002 (6 pages) 20vp8 (18 pages) 20xv10 (14 pages) 20_ASB_2011_MRO_Training_Section782299-1 (1 pages) 20_coc2008Chinese_Traditional (22 pages) |
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