| Specifications | ispLSI 2096VL Data Sheet ispLSI 2096VL Data Sheet ispLSI 2096VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
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| Specifications | ispLSI 2096VL Data Sheet ispLSI 2096VL Data Sheet ispLSI 2096VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
| Business section |
| Specifications | ispLSI 2096VL Data Sheet ispLSI 2096VL Data Sheet ispLSI 2096VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
| Outline | ispLSI 2096VL Data Sheet DC Electrical Characteristics AC Characteristics Pin Configuration: 128 TQFP Ordering Information |
| Suggested Link Details/Purchase | |
| Content | ispLSI ® 2096VL 2.5V In-System Programmable SuperFAST™ High Density PLD 2096vl_041 Features •SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC —4000 PLD Gates —96 I/O Pins, Six Dedicated Inputs —96 Registers —High Speed Global Interconnect —Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. —Small Logic Block Size for Random Logic —100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V and 2096VE Devices •2.5V LOW VOLTAGE 2096 ARCHITECTURE —Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) —85 mA Typical Active Current •HIGH PERFORMANCE E2CMOS® TECHNOLOGY —fmax = 165 MHz Maximum Operating Frequency —tpd = 5.5 ns Propagation Delay —Electrically Erasable and Reprogrammable —Non-Volatile —100% Tested at Time of Manufacture —Unused Product Term Shutdown Saves Power •IN-SYSTEM PROGRAMMABLE —2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) —Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic —Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality —Reprogram Soldered Devices for Faster Prototyping •100% IEEE 1149.1 BOUNDARY SCAN TESTABLE •THE EASE OF USE AND FAST SYSTEMSPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS —Enhanced Pin Locking Capability —Three Dedicated Clock Input Pins —Synchronous and Asynchronous Clocks —Programmable Output Slew Rate Control —Flexible Pin Placement —Optimized Global Routing Pool Provides Global Interconnectivity Description The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VL offers non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2096VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 . C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching Global Routing Pool (GRP) Output Routing Pool (ORP) Output Routing Pool (ORP) 0919/2096VL C7C4C5C6 A4A7A6A5 GLB Logic Array DQ DQ DQ DQ Output Routing Pool (ORP) Output Routing Pool (ORP) C3C0C1C2 B0B3B2B1 Output Routing Pool (ORP) Output Routing Pool (ORP) B7 B6 B4 B5 A0 A1 A3 A2 Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.January 2002 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com Functional Block Diagram Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm |
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| Following Datasheets | 209ce598-b279-4102-bb88-e7cefa29b57e (1 pages) 20ac79ba-16f5-4853-948f-f71c563c5232 (2 pages) 20clq045 (4 pages) 20G_SY-PQG208 (1 pages) 20GC001_1 (40 pages) 20GC004_1_1 (24 pages) 20GC014_Revb-1_1 (32 pages) 20GC015-1_RevB_1 (17 pages) 20gc017_1 (21 pages) 20KPA (4 pages) |
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