| Specifications | ispLSI 2032VL Data Sheet ispLSI 2032VL Data Sheet ispLSI 2032VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
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| Specifications | ispLSI 2032VL Data Sheet ispLSI 2032VL Data Sheet ispLSI 2032VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
| Business section |
| Specifications | ispLSI 2032VL Data Sheet ispLSI 2032VL Data Sheet ispLSI 2032VL, PLD, 2.5V, ISP, SuperFAST, high density Lattice Semiconductor |
| Outline | ispLSI 2032VL Data Sheet DC Electrical Characteristics AC Characteristics Pin Configuration: 44 TQFP Pin Configuration: 44 PLCC Pin Configuration: 48 TQFP Signal Configuration: 49 caBGA Ordering Information |
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| Content | ispLSI ® 2032VL 2.5V In-System Programmable SuperFAST™ High Density PLD 2032vl_031 Features •SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC —1000 PLD Gates —32 I/O Pins, Two Dedicated Inputs —32 Registers —High Speed Global Interconnect —Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. —Small Logic Block Size for Random Logic —100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V and 2032VE Devices •2.5V LOW VOLTAGE 2032 ARCHITECTURE —Interfaces With Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) —45 mA Typical Active Current •HIGH PERFORMANCE E2CMOS® TECHNOLOGY —fmax = 180 MHz Maximum Operating Frequency —tpd = 5.0 ns Propagation Delay —Electrically Erasable and Reprogrammable —Non-Volatile —100% Tested at Time of Manufacture —Unused Product Term Shutdown Saves Power •IN-SYSTEM PROGRAMMABLE —2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) —Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic —Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality —Reprogram Soldered Devices for Faster Prototyping •100% IEEE 1149.1 BOUNDARY SCAN TESTABLE •THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs —Enhanced Pin Locking Capability —Three Dedicated Clock Input Pins —Synchronous and Asynchronous Clocks —Programmable Output Slew Rate Control —Flexible Pin Placement —Optimized Global Routing Pool Provides Global Interconnectivity Functional Block Diagram Global Routing Pool (GRP)A0 A1 A3 Input Bus Output Routing Pool (ORP) A7 A6 A5 A4 Input Bus Output Routing Pool (ORP) A2GLB Logic Array DQ DQ DQ DQ 0139Bisp/2000 Description The ispLSI 2032VL is a High Density Programmable Logic Device containing 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VL offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 . A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.January 2002 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm |
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