ispLSI 2032E Data Sheet

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Specifications	ispLSI 2032E Data Sheet
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2032e_051 ispLSI ® 2032E In-System Programmable SuperFAST™ High Density PLD Features •SuperFAST HIGH DENSITY

Specifications	ispLSI 2032E Data Sheet
Outline	Features Functional Block Diagram Description Absolute Maximum Ratings DC Recommended Operating Conditions Capacitance Erase/Reprogram Specification Switching Test Conditions DC Electrical Characteristics External Timing Parameters Internal Timing Parameters ispLSI 2032E Timing Model Power Consumption Pin Descriptions Pin Configurations Part Number Description Ordering Information
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Content	2032e_051 ispLSI ® 2032E In-System Programmable SuperFAST™ High Density PLD Features •SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC —1000 PLD Gates —32 I/O Pins, Two Dedicated Inputs —32 Registers —High Speed Global Interconnect —Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. —Small Logic Block Size for Random Logic —100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices •HIGH PERFORMANCE E2CMOS® TECHNOLOGY —fmax = 225 MHz Maximum Operating Frequency —tpd = 3.5 ns Propagation Delay —TTL Compatible Inputs and Outputs —5V Programmable Logic Core —ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port —User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems —PCI Compatible Outputs (48-Pin Package Only) —Open-Drain Output Option —Electrically Erasable and Reprogrammable —Non-Volatile —Unused Product Term Shutdown Saves Power •ispLSI OFFERS THE FOLLOWING ADDED FEATURES —Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality —Reprogram Soldered Devices for Faster Prototyping •OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS —Complete Programmable Device Can Combine Glue Logic and Structured Designs —Enhanced Pin Locking Capability —Three Dedicated Clock Input Pins —Synchronous and Asynchronous Clocks —Programmable Output Slew Rate Control to Minimize Switching Noise —Flexible Pin Placement —Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com November 2003 Functional Block Diagram Global Routing Pool (GRP)A0 A1 A3 Input Bus Output Routing Pool (ORP) A7 A6 A5 A4 Input Bus Output Routing Pool (ORP) A2GLB Logic Array DQ DQ DQ DQ 0139Bisp/2000 Description The ispLSI 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides com- plete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmabil- ity and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 . A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually
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