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| Content | Design Solutions for Preventing Process Induced ESD Damage during Manufacturing of Interconnects J. Ackaert1, B. Greenwood 2 1)On semiconductor, Westerring 15, 9700 Oudenaarde, Belgium 2)On semiconductor USA Tel: (32)-55-332343 Email: jan.ackaert@onsemi.com 1. Abstract ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS [1]. Little is known however on the impact of simple wafer cleaning/spraying as used frequently during the wafer manufacturing itself. In many cases these processes do include high risks of generating electrostatic charge; subsequent discharge into devices and can easily induce ESD-like events internally in the interconnect circuitry of a device. In this paper, charging induced damage (CID) into common metal interconnect is reported. The damage is caused by the build up of charges on a resist surface during a water rinsing step. This charging is inducing a mirror charge on the interconnect circuitry and results in a discharge through the inter metal dielectric layer (IMD) towards a grounded structure. This CID can lead to direct severe yield loss. In milder cases the damage is difficult to detect but is proven to result in reliability issues. The charging has been detected, measured and evaluated with the help of a non contact surface potential measurement. The phenomena has been characterized and quantified. This paper is describing the occurrence of the failures, the design of the test structures, the measurement results. This work is concluding on how a design can be made safe from ESDFOS during processing by applying the popper layout rules. 1. Introduction In common understanding, electrostatic discharge (ESD) is known as a charge introduction into or out from a semiconductor device via its pins, following specific models like HBM (human body model), CDM (charge device model) or MM (machine model). All usual methods to avoid ESD are focused on device design (pad protective structures) and ESD protection zones in the production, where most attention is paid to antistatic clothing, shoes, workplaces, floors and robotic handling [1]. Lots of effort has been done in the last three decades in order to improve in these areas, but much less activities were done considering ESD risks generated by inherent processing steps such as cleaning and coating itself. In several investigations failures were observed resulting from surface ESD-impacts. Direct discharge into the device interlevel dielectric (ILD) caused defects raging between very small shorts of the top metals and large craters in the ILD. In such case, the ‘‘classical” way of ESD via the pads was bypassed, such eliminating the pad protective structures. Earlier work describes charging affects specific for metal-insulator-metal capacitors devices (MIMC) [2]. For the first time however a charging phenomena is describe occurring simple during spin rinsing with DI water affecting common metal interconnects in semiconductor devices. Fig.1: SEM picture of severe defects after an internal ESD event between interconnect networks. The blue are the remain of the metal lines This paper is describing how the charging has been detected, measured and analysed with the help of a non contact surface potential measurement. The phenomena has been characterized quantified. Proposals are made on how to make a layout failsafe from ESDFOS by design. 2. Experimental The defects were discovered right after the definition of the via mask on top of the ILD covering the interconnect networks. The defect itself is located where the a floating partially processed network is in close proximity to a grounded network already connected to silicon. In order to determine the parameters that have an affect of the occurrence of the discharging, special set of test structures have been designed and manufactured. As depicted in Fig. 2, a |
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| Following Datasheets | ICL_B57211P_P11 (14 pages) ICL_B57213P_P13 (14 pages) ICL_B57153_S153 (14 pages) ICL_B57235_S235 (14 pages) ICL_B57236_S236 (14 pages) ICL_B57237_S237 (14 pages) ICL_B57238_S238 (14 pages) ICL_B57364_S364 (14 pages) ICL_B57464_S464 (14 pages) ICM4 (2 pages) |
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